1. Field of the Invention
The present invention relates generally to the chemical mechanical polishing (CMP) of semiconductor wafers, and more particularly, to techniques for polishing end-point detection.
2. Description of the Related Art
In the fabrication of semiconductor devices, there is a need to perform CMP operations, including polishing, buffing and wafer cleaning. Typically, integrated circuit devices are in the form of multi-level structures. At the substrate level, transistor devices having diffusion regions are formed. In subsequent levels, interconnect metallization lines are patterned and electrically connected to the transistor devices to define the desired fictional device. As is well known, patterned conductive layers are insulated from other conductive layers by dielectric materials, such as silicon dioxide. At each metallization level there is a need to planarize metal or associated dielectric material. Without planarization, fabrication of additional metallization layers becomes substantially more difficult due to the higher variations in the surface topography. In other applications, metallization line patterns are formed in the dielectric material, and then metal CMP operations are performed to remove excess metallization, e.g., such as copper.
In the prior art, CMP systems typically implement belt, orbital, or brush stations in which belts, pads, or brushes are used to scrub, buff, and polish a wafer. Slurry is used to facilitate and enhance the CMP operation. Slurry is most usually introduced onto a moving preparation surface, e.g., belt, pad, brush, and the like, and distributed over the preparation surface as well as the surface of the semiconductor wafer being buffed, polished, or otherwise prepared by the CNP process. The distribution is generally accomplished by a combination of the movement of the preparation surface, the movement of the semiconductor wafer and the friction created between the semiconductor wafer and the preparation surface.
FIG. 1A shows a cross sectional view of a dielectric layer 102 undergoing a fabrication process that is common in constructing damascene and dual damascene interconnect metallization lines. The dielectric layer 102 has a diffusion barrier layer 104 deposited over the etch-patterned surface of the dielectric layer 102. The diffusion barrier layer, as is well known, is typically titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination of tantalum nitride (TaN) and tantalum (Ta). Once the diffusion barrier layer 104 has been deposited to the desired thickness, a copper layer 104 is formed over the diffusion barrier layer in a way that fills the etched features in the dielectric layer 102. Some excessive diffusion barrier and metallization material is also inevitably deposited over the field areas. In order to remove these overburden materials and to define the desired interconnect metallization lines and associated vias (not shown), a chemical mechanical planarization (CMP) operation is performed.
As mentioned above, the CMP operation is designed to remove the top metallization material from over the dielectric layer 102. For instance, as shown in FIG. 1B, the overburden portion of the copper layer 106 and the diffusion barrier layer 104 have been removed. As is common in CMP operations, the CMP operation must continue until all of the overburden metallization and diffusion barrier material 104 is removed from over the dielectric layer 102. However, in order to ensure that all the diffusion barrier layer 104 is removed from over the dielectric layer 102, there needs to be a way of monitoring the process state and the state of the wafer surface during its CMP processing. This is commonly referred to as end-point detection. In multi-step CMP operations there is a need to ascertain multiple end-points (e.g., such as to ensure that Cu is removed from over the diffusion barrier layer; and to ensure that the diffusion barrier layer is removed from over the dielectric layer). Thus, end-point detection techniques are used to ensure that all of the desired overburden material is removed. A common problem with current end-point detection techniques is that some degree of over-etching is required to ensure that all of the conductive material (e.g., metallization material or diffusion barrier layer 104) is removed from over the dielectric layer 102 to prevent inadvertent electrical interconnection between metallization lines. A side effect of improper end-point detection or over-polishing is that dishing 108 occurs over the metallization layer that is desired to remain within the dielectric layer 102. The dishing effect essentially removes more metallization material than desired and leaves a dish-like feature over the metallization lines. Dishing is known to impact the performance of the interconnect metallization lines in a negative way, and too much dishing can cause a desired integrated circuit to fail for its intended purpose.
FIG. 1C shows a prior art belt CMP system in which a pad 150 is designed to rotate around rollers 151. As is common in belt CMP systems, a platen 154 is positioned under the pad 150 to provide a surface onto which a wafer will be applied using a carrier 152 as shown in FIG. 113. One way of performing end-point detection is to use an optical detector 160 in which light is applied through the platen 154, through the pad 150 and onto the surface of the wafer 100 being polished. In order to accomplish optical end-point detection, a pad slot 150a is formed into the pad 150. In some embodiments, the pad 150 may include a number of pad slots 150a strategically placed in different locations of the pad 150. Typically, the pad slots 150a are designed small enough to minimize the impact on the polishing operation. In addition to the pad slot 150a, a platen slot 154a is defined in the platen 154. The platen slot 154a is designed to allow the optical beam to be passed through the platen 154, through the pad 150, and onto the desired surface of the wafer 100 during polishing.
By using the optical detector 160, it is possible to ascertain a level of removal of certain films from the wafer surface. This detection technique is designed to measure the thickness of the film by inspecting the interference patterns received by the optical detector 160. Although optical end-point detection is suitable for some applications, optical end-point detection may not be adequate in cases where end-point detection is desired for different regions or zones of the semiconductor wafer 100. In order to inspect different zones of the wafer 100, it is necessary to define several pad slots 150a as well as several platen slots 154a. As more slots are defined in the pad 150 and the platen 154, there may be a greater detrimental impact upon the polishing being performed on the wafer 100. That is, the surface of the pad 150 will be altered due to the number of slots formed into the pad 150 as well as complicating the design of the platen 154.
Additionally, conventional platens 154 are designed to strategically apply certain degrees of back pressure to the pad 150 to enable precision removal of the layers from the wafer 100. As more platen slots 154a are defined into the platen 154, it will be more difficult to design and implement pressure applying platens 154. Accordingly, optical end-point detection is generally complex to integrate into a belt CMP system and also poses problems in the complete detection of end-point throughout different zones or regions of a wafer without impacting the CMP system""s ability to precision polish layers of the wafer.
FIG. 2A shows a partial cross-sectional view of an exemplary semiconductor chip 201 after the top layer has undergone a copper CMP process. Using standard impurity implantation, photolithography, and etching techniques, P-type transistors and N-type transistors are fabricated into the P-type silicon substrate 200. As shown, each transistor has a gate, source, and drain, which are fabricated into appropriate wells. The pattern of alternating P-type transistors and N-type transistors creates a complementary metal dielectric semiconductor (CMOS) device.
A first dielectric layer 202 is fabricated over the transistors and substrate 200. Conventional photolithography, etching, and deposition techniques are used to create tungsten plugs 210 and copper lines 212. The tungsten plugs 210 provide electrical connections between the copper lines 212 and the active features on the transistors. A second dielectric layer 204 may be fabricated over the first dielectric layer 202 and copper lines 212. Conventional photolithography, etching, and deposition techniques are used to create copper vias 220 and copper lines 214 in the second dielectric layer 204. The copper vias 220 provide electrical connections between the copper lines 214 in the second layer and the copper lines 212 or the tungsten plugs 210 in the first layer.
The wafer then typically undergoes a copper CMP process to planarize the surface of the wafer as described with reference to FIGS. 1A-1D, leaving an approximately flat surface (with possible dishing, not shown here, but illustrated with reference to FIG. 1B). After the copper CMP process, the wafer is cleaned in a wafer cleaning system.
FIG. 2B shows the partial cross-sectional view after the wafer has undergone optical end-point detection as discussed with reference to FIGS. 1C and 1D. As shown, the copper lines 214 on the top layer have been subjected to photo-corrosion during the detection process. The photo-corrosion is believed to be partially caused by light photons emitted by the optical detector and reach the P/N junctions, which can act as solar cells. Unfortunately, this amount of light, which is generally normal for optical detection can cause a catastrophic corrosion effect.
In this cross-sectional example, the copper lines, copper vias, or tungsten plugs are electrically connected to different parts of the P/N junction. The slurry chemicals and/or chemical solutions applied to the wafer surface, can include electrolytes, which have the effect of closing an electrical circuit as electrons exe2x88x92 and holes h+ are transferred across the P/N junctions. The electron/hole pairs photo-generated in the junction are separated by the electrical field. The introduced carriers induce a potential difference between the two sides of the junction. This potential difference increases with light intensity. Accordingly, at the electrode connected to the P-side of the junction, the copper is corroded: Cuxe2x86x92Cu2++2exe2x88x92. The produced soluble ionic species can diffuse to the other electrode, where the reduction can occur: Cu2++2exe2x88x92xe2x86x92Cu. Note that the general corrosion formula for any metal is Mxe2x86x92Mn++nexe2x88x92, and the general reduction formula for any metal is Mnxe2x88x92+nexe2x88x92xe2x86x92M. For more information on photo-corrosion effects, reference can be made to an article by A. Beverina et al., xe2x80x9cPhoto-Corrosion Effects During Cu Interconnection Cleanings,xe2x80x9d to be published in the 196th ECS Meeting, Honolulu, Hi. (October 1999). This article is hereby incorporated by reference.
Unfortunately, this type of photo-corrosion displaces the copper lines and destroys the intended physical topography of the copper features, as shown in FIG. 2B. At some locations on the wafer surface over the P-type transistors, the photo-corrosion effect may cause corroded copper lines 224 or completely dissolved copper lines 226. In other words, the photo-corrosion may completely corrode the copper line such that the line no longer exists. On the other hand, over the N-type transistors, the photo-corrosion effect may cause copper deposit 222 to be formed. This distorted topography, including the corrosion of the copper lines, may cause device defects that render the entire chip inoperable. One defective device means the entire chip must be discarded, thus, decreasing yield and drastically increasing the cost of the fabrication process. This effect, however, will generally occur over the entire wafer, thus destroying many of the chips on the wafer. This, of course, increases the cost of fabrication.
In view of the foregoing, there is a need for CMP end-point detection systems that do not implement optical detectors and enable precision end-point detection to prevent dishing and avoid the need to perform excessive over-polishing.
Broadly speaking, the present invention fills these needs by providing end-point detection systems and methods to be used in the chemical mechanical polishing of substrate surface layers. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device or a method. For example, the present invention can be used with linear belt pad systems, rotary pad systems, as well as orbital pad systems. Several inventive embodiments of the present invention are described below.
In one embodiment, a chemical mechanical polishing system is disclosed. The system includes a polishing pad that is configured to move linearly from a first point to a second point. A carrier is also included and is configured to hold a substrate to be polished over the polishing pad. The carrier is designed to apply the substrate to the polishing pad in a polish location that is between the first point and the second point. A first sensor is located at the first point and oriented so as to sense an IN temperature of the polishing pad, and a second sensor is located a the second point and oriented so as to sense an OUT temperature of the polishing pad. The sensing of the IN and OUT temperatures is configured to produce a temperature differential that when changed indicates a removal of a desired layer from the substrate.
In another embodiment, a method for monitoring end-point for chemical mechanical polishing is disclosed. The method includes providing a polishing pad belt that is configured to move linearly, and applying a wafer to the polishing pad belt at a polishing location so as to remove a first layer of material from the wafer. The method further includes sensing a first temperature of the polishing pad belt at an IN location that is linearly before the polishing location and sensing a second temperature of the polishing pad belt at an OUT location that is linearly after the polishing location. Then, a temperature differential is calculated between the second temperature and the first temperature. A change in the temperature differential is then monitored, such that the change in temperature differential is indicative of a removal of the first layer from the wafer. Wherein the first layer can be any layer that is fabricated over a wafer, such as dielectric, copper, diffusion barrier layers, etc.
In still another embodiment, a method for monitoring an end-point of material removal from a wafer surface is disclosed. The method includes: (a) providing a polishing pad that is configured to move linearly; (b) applying a wafer to the polishing pad at a polishing location so as to remove a layer of material from the wafer; (c) sensing a first temperature of the polishing pad at a first location that is before the polishing location; (d) sensing a second temperature of the polishing pad at a second location that is after the polishing location; and (e) calculating a temperature differential between the second temperature and the first temperature.
In another embodiment, an end-point detection method is disclosed. The method includes: (a) providing a polishing pad; (b) applying a wafer to the polishing pad at a polishing location so as to remove a first layer of material from the wafer; (c) sensing a first temperature of the polishing pad at an IN location that is before the polishing location; (d) sensing a second temperature of the polishing pad at an OUT location that is after the polishing location; (e) calculating a temperature differential between the second temperature and the first temperature; and (f) monitoring a change in the temperature differential, the change being indicative of a removal of the first layer from the wafer. Wherein, the pad is one of a belt pad, a table pad, a rotary pad, and an orbital pad.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the present invention.